1. Field of the Invention
This invention relates to a semiconductor memory, and more particularly to a semiconductor memory using a serial address pointer such as a sequential-access or serial-access memory, a VRAM (video RAM), or a field memory.
2. Description of the Related Art
Conventional sequential-access memories use a serial address pointer for specifying an address in a memory array to be accessed sequentially.
The address pointer, which is placed to one side of a memory cell array, is normally composed of a shift register containing fixed n stages of D flip-flop circuits series-connected, or of a log 2.sup.n -stage binary counter section and a decoder section with a fixed number of stages for decoding the output signal from each stage of the binary counter section.
In conventional sequential-access memories using a serial address pointer as mentioned above, there has been no redundancy in the memory cell array.
If redundancy techniques were introduced to the sequential-access memories like ordinary RAMs, semiconductor memories with a certain memory capacity would be realized by providing spare rows and/or columns in a particular location in the memory cell array and replacing the defective row and/or column, if any, with a spare row and/or column to remedy the faulty chip.
In this case, if the number of defective rows and/or columns were larger than that of spare rows and/or columns, or if spare rows and/or columns themselves were defective, it would be impossible to remedy the faulty chip, resulting in a poorer yield. Further, the remaining good area except the defective rows and/or columns cannot be used effectively.
To replace the defective rows and/or columns with spare rows and/or columns in the memory cell array, an address-replacing logic circuit is used to replace row addresses and/or column addresses.
Here, there arise the problem that the address replacing logic circuit requires a complicated configuration in order to replace many defective rows and/or columns with spare rows and/or columns.